Firmware
Firmware was written in VHDL. Producer of the CPLD provides free development tools. For further informations check Xilinx website ISE WebPACK, ModelSim XE.
Although used FPGA XC95288XL is the biggest from the CPLD XL family, it is still not big enough to implement all logic and therefore several versions of firmware exist.
Currently exist following types of firmware:
Timeanalysis (1.x)
Most commonly used mode when sample is taken upon every clock pulse. In this mode 32 channels can be simultaneously sampled.
Documentation is included in the firmware release. Latest version also available here:
HTML,
PDF
Source is also available via the CVS. For download use command:
cvs -d:pserver:anonymous@cvs.sourceforge.net:/cvsroot/minila login cvs -z3 -d:pserver:anonymous@cvs.sourceforge.net:/cvsroot/minila co -r fw_1_7 fw_timeanalysis
Stateanalysis (2.x)
In this mode memory data bus is divided into two halves. Lower-half of the memory bus (bits 0 to 15) is used for storing samples and upper half (bits 16 to 31) for timestamps. Samples are stored only in the case of difference with previous sample and timestamp then determines number of clocks from previous data change. This provides some sort of RLE compression and allows to extend time of measurement for slow changing signals. Disadvantage is limitation of simultaneously sampled channels to 16.
Documentation is included in the firmware release. Latest version also available here:
HTML,
PDF
Source is also available via the CVS. For download use command:
cvs -d:pserver:anonymous@cvs.sourceforge.net:/cvsroot/minila login cvs -z3 -d:pserver:anonymous@cvs.sourceforge.net:/cvsroot/minila co -r fw_2_2 fw_stateanalysis
LED tester
LED tester is a simple firmware created in order to quickly test the functionality of miniLA hardware. It just implements 26 bits wide counter with its outputs driving status LEDs. Having CPLD programmed you should see LEDs blinking (bit 0 is connected to D5, bit 10 to D4 and bit 25 to D3).
> download <CPLD programming:
Prior to use, the CPLD has to be programmed with appropriate firmware. This text describes programming using program iMPACT (part of the ISE WebPACK) and Xilinx LPT JTAG programmer (schematic).
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Connect TDI, TDO, TMS, TCK, VCC and GND between miniLA and programmer. Power up the miniLA.
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Start program iMPACT (Start -> Programs -> Xilinx ISE -> Accessories -> iMPACT
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Choose Configure Devices, click NEXT
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Choose Boundary-Scan mode, click NEXT
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Choose Automatically connect to cable ..., click NEXT
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Now your programmer gets detected and picture of chip will show. Right click on the chip, choose Assign New Configuration File, browse to the *.jed file a click Open
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Right click on the chip, choose Program.... In following window only options Erase Before Programming and Verify should be selected. Click OK.
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CPLD will be programmed.