miniLA
Communication Protocol &
Specification

Stateanalysis

Firmware version 2.2

Communication protocol

miniLA Interface

The miniLA communicates via parallel port in standard EPP mode. EPP mode is not described here. More information can be found for example on page http://www.beyondlogic.org/epp/epp.htm.

EPP Memory map

There are several registers for control of the miniLA mapped in the EPP address range. Mapping is shown in the table below:

*) when reading from unused entry, the outputs are in high impedance

Description of EPP registers

• Control Register

BS1:BS0 Byte selector, defines byte order when reading data from data register. After every read from data register the byte selector is automatically incremented.

data(15:0) is the channel sample value, time(15:0) is number of clocks of sample duration decreased by 1.

STOP Writing of logic 1 interrupts the sampling.

AINC Writing of logic 1 enables the auto increment of memory address. The memory address is incremented when bit is 1, data from data register are read and current bytesel has value “11”.

PCLK Writing of logic 1 increments the memory address. Bit is cleared automatically. Active only when bit DONE active or timebase set to "11111".

CLR Writing of logic 1 resets the miniLA. It doesn't affect the EPP registers.

RUN Writing of logic 1 starts the sampling.

• Trigger Events Counter Register

J3:J0 Bits J3:J0 define number of trigger hits before the postrigger data are stored decreased by 1.

• Trigger Length Counter Register

K3:K0 Bits define the minimal number of clocks for which the input signal must be stable to be considered as trigger hit. Value K3:K0 = "0000" is not valid.

• Pre/Post trigger Register

P3:P0 Bits P3:P0 define length of the pretrigger/postrigger in 8K steps.

PRD Pretrigger Disable - Writing of logic 1 disables the pretrigger.

PRD	P3:P0	Pretrigger length	Postrigger length	Trigger position
0	0000	8K	120K	8K
0	0001	16K	112K	16K
0	0010	24K	116K	24K
.	.	.	.	.
0	1110	120K	8K	120K
0	1111*	--	--	--
1	0000	0	8K	1
1	0001	0	16K	1
1	0010	0	24K	1
.	.	.	.	.
1	1111	0	128K	1

*) not supported setting

• Trigger Value Registers

adr 5:

adr 6:

X15:X0 Bits X15:X0 are compared with input data D15:D0. The trigger hit occurs if the result of comparison is true.

• Trigger Edge Registers

adr 7:

adr 8:

E15:E0 Bits E15:E0 defines whether input bits D15:D0 are checked for edge (1) or for value (0). In cooperation with trigger value register it defines rising edge (bit in value reg 1) or falling edge (bit in value reg 0) sensitivity.

Note1: Only unmasked bits can be set to 1. In control software this can be accommodated by command like edge_reg=edge_reg&mask_reg.

Note2: When edge detection is used, trigger length register should be set to 1.

• Trigger Mask Registers

adr 9:

adr 10:

M15:M0 Bits M15:M0 defines which bits in Trigger Value Registers (X15:X0) are tested or ignored. When at logic 1, the bit is tested, otherwise ignored.

• Trigger Control Register

ETV Value for comparison with external trigger input.

ETS Writing of logic 1 enables external trigger input and disables internal trigger. Conditions defined by Trigger Events Counter and Trigger Length Counter applies also for external trigger.

IIT Writing of logic 1 inverts the result of internal trigger (trigger event occurs when result of comparation between data bus and Trigger Value Reg (masked) is FALSE).

• Data Register

Depending on the current state of the miniLA, this register provides access either to input data or to data stored in memory during sampling. Selection of byte order is defined by bits BS1 and BS0 in control register.

RUN	Data available at Data Register
0	Input data (delayed by 3 clocks)
1	Data from memory

• Status and Version Register

FW3:FW0 Bits FW3:FW0 defines the CPLD firmware version.

HW2:HW0 Bits HW2:HW0 defines the hardware version.

DONE Status bit, logic 1 when sampling completed or interrupted.

• Status Register 2

SCT Sample Counter Watermark – Used for data retrieval, see section Recommended Command Sequence.

TRIG Logic 1 indicates successful detection of trigger condition during sampling.

CLR Copy of bit CLR in control register. Logic 1 indicates the miniLA is in reset state.

RUN Copy of bit RUN in control register. Logic 1 indicates the start of sampling was enabled. Bit is not cleared when sampling is completed or interrupted.

DONE Logic 1 indicates that the sampling was completed or interrupted and the data can be read from the memory.

Recommended command sequence

• Initialization

1. Write a value 0x40 into Control Register. This puts the miniLA in reset state.

2. Write appropriate values in all remaining registers (registers are not affected by miniLA reset, all registers are set to 0x00 at power-up)

3. At this stage the input data of the miniLA can be accessed by reading the data register.

4. Sampling starts by writing a value 0x80 into Control Register.

• Data sampling

1. During the sampling period, the input data can be accessed in the same way as in the initialization phase.

2. Periodically read Status Register (or Status Register 2) and wait until the bit DONE is at logic 1.

3. If it is necessary to interrupt the sampling, write value 0x08 into Control Register.

• Data retrieving

1. Data can be retrieved from the memory only when the status bit DONE is at logic 1.

2. Write value 0x1F to Pre/Post trigger register.

3. Read Status Register 2 and check the value of bit SCT.

4. Data are ready for read if the value of bit SCT is at logic 1. If it is not, increment the memory address (by writing value 0x20 into control register) so many times (n times) until bit SCT is at logic 1.

5. Generate 1 additional clock pulse (write value 0x20 into control register), enable auto increment (write 0x10 into control register) and then read 128K-(n+1) longwords of data by successive reading of the Data Register.

Specification